DOI: 10.5176/978-981-08-7654-8_R-27

Authors: Hsin-Liang Lin and Jong-Jiann Shieh

Reduce power consumption in the current multi-core processors is more important than performance enhancement. On chip cache memory (instruction cache and data cache) accounted for nearly 45% of power consumption in a processor, reducing the power consumption of cache memory will be able to significantly reduce processor power consumption. We propose a new level-0 cache memory in the memory hierarchy. The cache contains a filter cache and a victim cache. The proposed scheme reduces the power consumption in the instruction cache and data cache by reducing the number of accesses to the level-1 and level-2 cache. We use a simulation infrastructure base on SimpleScalar, sim-wattch, and CACTI to evaluate our proposed scheme. Our structure saves 28% power consumption as compared to the original memory architecture without victim cache and filter cache in multi-core processor. Simulation results show that the proposed technique improve the performance up to 15% compared to the conventional cache architecture.

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