Authors: Laxmi Kumre, Dr Ajay Somkuwar, Dr Ganga Agnihotri
Design of modified booth encoded multiplier using GDI technique is presented in this paper. Today, low power design has become the main consideration in digital VLSI circuit design. The modified booth encoded multiplier with pipeline architecture using GDI technology proposed here that allows reduction in power, transistor count and access time. It also provides full swing while maintaining low complexity of logic design. Performance comparison of proposed multiplier with traditional CMOS and various pass transistor logic design techniques is presented. The different techniques are compared with respect to the layout area, number of devices, gate area, delay and power dissipation.