DOI: 10.5176/978-981-08-7240-3_G-06

Authors: Yeong-Chang Maa, Mao-Hsu Yen, Shu-Ming Kuo and Guan-Luen Lee


With the ever increasing needs of power aware architecture and circuit design in recent years, how to reduce the power consumption of processors without sacrificing performance has become an important issue. In this paper, we propose a new method for low power branch prediction - Hedging Filter, which combines filtering scheme reducing dynamic power consumption with hedging prediction mechanism lowering static power dissipation. We analyze and empirically study this proposed scheme embodied in the Sentry Table - Complementary Branch Prediction combo with respect to critical path delay, performance,hardware overhead and power consumption. Hedging Filter not only preserves critical path delay and prediction accuracy, but also contributes to the savings of dynamic and static power. From our evaluation, presuming equivalent or superior performance with respect to traditional counterparts, the proposed method reduces branch prediction hardware cost by up to 71{6e6090cdd558c53a8bc18225ef4499fead9160abd3419ad4f137e902b483c465} and power saving by up to 79{6e6090cdd558c53a8bc18225ef4499fead9160abd3419ad4f137e902b483c465} respectively.


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