Evaluation of Application Mapping for Network-on-Chips

DOI: 10.5176/978-981-08-7654-8_R-14

Authors: M. Jalal, Z. Shirmohammadi, A. Patooghy and S. G. Miremadi

Abstract:
Mapping of tasks on the cores of a Network-on-Chip(NoC) has direct impact on the efficiency of the network. This paper provides a comprehensive study regarding application mapping for NoCs to clarify their pros and cons. The study considers different aspects including performance, power consumption, and reliability of mappings. Four mappings named NMAP, RMAP, Random, and Adhoc are used in this study by the means of a cycle accurate NoC simulator. Our study shows that the RMAP provides the maximum reliability for NoC with a low performance overhead. On the other hand, Random mapping requires the lowest time to complete mapping of the task on the chip. The power estimation patch of Orion is used in the simulation to explore the power consumption of a typical NoC using any of the mentioned mappings. Simulations are done for three different benchmarks i.e., MPEG, VOPD, and OPD application graphs.