DOI: 10.5176/2251-1652_ADPC12.04

Authors: Tariq Ahmad, Seiyang Yang, Maciej Ciesielski and Dusung Kim


Application of parallel discrete event simulation(PDES) to hardware design verification looks promising, given the complexity of today’s hardware designs. Unfortunately, the challenges imposed by suboptimal design partitioning,synchronization and communication overhead, and load balancing, render this approach largely ineffective. To this end,this paper presents a new and effective solution to PDES for hardware design verification. It is based on a novel idea of spatial parallelism using accurate prediction. The proposed approach is immune to suboptimal partitioning as it exploits the inherent hierarchy present in the design. In addition, it reduces the communication and synchronization overhead by using accurate prediction model. We demonstrate the effectiveness of our approach on several industrial hardware designs.

Keywords: parallel simulation; event driven simulation; verilog;RTL; gate-level; timing verification.


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